Hardware Implementation of a High Efficiency and High-Speed Squaring Architecture



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Submitted Jun 25, 2022
Published Aug 4, 2022
10.24018/compute.2022.2.4.71

Abstract viewed = 334 times

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This paper presents the design of a high speed and simple squaring structure based on half adder and full adder. The proposed architecture consists of three main steps; simplification of the squaring structure, calculation and transferring of the carry bit to the next part, and finally, applying the modified Wallace Tree Adder to calculate the summation of the products. The proposed squaring architecture is formed only by 13 half adders and 20 full adders for 8-bit squaring which has the lowest complexity compared to other works. The proposed structure is modeled by using Field-Programmable Gate Array (FPGA) and has been successfully synthesized and implemented with Xilinx Spartan-6 and Virtex-4 FPGA. Simulation results show that the proposed structure has high speed and excellent performance with low power consumption while having the lowest propagation delay (3.25 ns) and acceptable hardware utilization compared to existing squaring models. The gate-level design of 8-bit squaring is implemented using Cadence layout tools in 65 nm CMOS technology which has a total area of 0.095 mm2.

Keywords: Field-Programmable Gate Array (FPGA), full adder (FA), gate-level design, half adder (HA), Wallace Tree Adder, Xilinx Spartan-6, Xilinx Virtex-4, 65 nm CMOS technology, 8-bit squaring

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